**Objectives**

In part I we have generated VHDL code from a State Diagram. We will now simulate the state diagram in order to debug it, and to ensure that it behaves as expected. In part III we will implement the VHDL code of part I in actual FPGA Spartan 3 Starter kit board.

**Using Statebench**

Before implementing our logic in our Spartan 3 Board we need to make sure that the State Diagram that we have designed will be behaving as expected by simulating it. With StateBench we can go through our design one clock cycle at a time, changing inputs and verifying outputs.

Our State Diagram of part I looks like this:

In order to be able to simulate it, we need to add a reset. In StateCAD activate Add reset:

Now add reset to the state diagram:

The following window will pop up:

Press No button to choose synchronous. We are now ready to simulate.

Click the StateBench button:

StateBench window will open:

Click the Reset button. We will now see the initial state:

We then need to add more clock cycles, clicking onto:

The result will be as shown:

We will next change input by double clicking on a time line position of input and a cursor line will appear as shown with a pop up window to assign a value:

Change the value to decimal 1 (001). The resulting window will pop up:

We will choose No to change input value to 001 henceforth. And the result will be:

**NOTE:** By default the rightmost edge of the clock before the point chosen will be indicating the new value (decimal 1). SIREN is still off, and we remain in STATE0.

Change values the same way to 2 (010) , 3 (011) and 4 (100). The state will continue to be STATE0 and SIREN will not sound, i.e. it will be 0 (zero).

Nowzn if we add input value 5 (101) at a different time line as shown:

The following window will pop up:

Choose again No to change values henceforth.

Around less than 10 cycles later (about 1ms later) there will a transition to STATE1 and SIREN will be sounding. i.e. it will be 1. To view better the transition, add more clock cycles by Â clicking onto:

And now you can view better what is happening:

Change again by double clicking at time line edge of input to obtain the following result:

Introduce 4 (100) i.e. door is closed (B=0) and again the following window will pop up:

Choose No to maintain the input value henceforth. The result will be as shown i.e. that the state remains itself as STATE1 and SIREN is still sounding:

The graph means that if we rapidly shut the door (returning to 100 condition) Â at 86ns (1300 minus 1214ns) Â the SIREN will continue to sound, and the system will maintain itself at STATE1. Change the condition again to another value as shown:

Now at a different time line do the same procedure as before and change the condition of input to 1 (001)

To view bettera, add clock cycles by pressing the button:

Our better view will be something similar to shown below:

At about less than 10 cycles i.e. about 1ms, there will be transition to STATE0 and SIREN will not sound anymore. We have returned to the first state, i.e. STATE0. If we repeat the input conditions as we did before, we will prove that a transition occurs only to STATE1 when input is either 5 (101) or 6 (110) Â or 7 (111).

**Conclusions:**

StateBench allows to simulate a state diagram by going through our design one clock cycle at a time, changing inputs and verifying output.

Our simulation has proven that the State Diagram we designed in part I is behaving as expected. We need now to implement and to test in our Digilent Spartan 3 board, the VHDL we generated in part I..

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