Tag Archives: Finite State Machine

Finite-State Machine Design of a Simple Car Security Alarm on a Xilinx FPGA – Part III

Objectives Implement  on actual hardware, a Xilinx Spartan 3 Starter kit board from Digilent, with VHDL code generated after having designed a simple car security alarm using StateCAD in part I. Requirements – Xilinx ISE Design Suite 14.2 – Digilent Spartan 3 Starter Kit board. Car Security Alarm Specifications … Continue reading

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Finite-State Machine Design of a Simple Car Security Alarm on a Xilinx FPGA – Part II

Objectives In part I we have generated VHDL code from a State Diagram. We will now simulate the state diagram in order to debug it, and to ensure that it behaves as expected. In part III we will implement the … Continue reading

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Finite-State Machine Design of a Simple Car Security Alarm on a Xilinx FPGA – Part I

Objectives Finite-state machine (FSM) or finite-state automaton design of a simple car security alarm using StateCAD, and implementation  on a Digilent FPGA Spartan 3 Starter kit board.. In this part we will generate the VHDL code. In part II we will simulate and in part III we … Continue reading

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