RedAcacia

Objectives

Implement  on actual hardware, a Xilinx Spartan 3 Starter kit board from Digilent, with VHDL code generated after having designed a simple car security alarm using StateCAD in part I.

Requirements

– Xilinx ISE Design Suite 14.2
– Digilent Spartan 3 Starter Kit board.

Car Security Alarm Specifications

We wil devise a simple Car Security Alarm on actual hardware, a Digilent Spartan Starter KIt board, that will sound a siren ( LD0 will switch on in our Spartan 3 board) if the car alarm system has been energized i.e. armed (A=1, that is SW7 in our Spartan 3 board ) and the door is open (B=1, that is SW1 in our Spartan 3 board) and / or an ultrasonic sensor signals movement inside the car (C=1, that is SW0 in our Spartan 3 board).

Implementation on a FPGA

Launch Xilinx ISE  Design Suite, get into the Project Navigator, and start a New Projectpressing the button for New Project. Xilinx ISE Project Navigator controls all aspects of the development flow of our FPGA. We will use it to launch all development tasks.

Give the project a name such as Car_Sec and fill all the fields appropriately, including pointing to the drive and directory in your PC where you will keep the project files:

Click on Next button and the following window will open:

Do the required changes as shown on the image and click Next button. The following window will open:

Click Finish button. The Project Navigator will show an empty view of the Hierachy window of our project:

Now we add the VHDL source we have generated in part I:

The following window will open which will hopefully do a sucessful adding of source:

Press Ok button.

The Project Navigator will show a summary of what has been done so far and the source code will show up in Hierarchy window. Highlight the Car_Sec.vhd file and double click on it:

The full VHDL code will be shown in the right window of our Project Navigator:

We are now ready to check syntax, and do further preparations for implementation.

In the Processes window we run Check Syntax

The results hopefully will be Ok as shown:

We will next see our schematic. We will first run Create Schematic Symbol in Processes window:

Now run View RTL Schematic in Processes window:

Viewer Startup Mode window will pop up, where we will choose the second choice as shown:

Click Ok. In the right window of Project Navigator we will see the main schematic:

If we click the block diagram, we will see:

By clicking LUT4 block we will see the logic circuit:

We are now ready to create contraints, i.e. configuration of inputs and outputs in our Digilent Spartan 3 Starter kit board. In Processes window run I/O Pin Planning (PlanAhead):

A window will pop up to tell us that no constraints file have been created:

We click Yes button. PlanAhead will open with Welcome to Plan Ahead window popping up:

After tcl file has run automatically, we have to close this window and concentrate on I/O Ports window of PlanAhead:

Clicking on ABC and Scalar ports we will expand these folders. And we start to introduce constraints referring to our Digilent Spartan 3 Starter kit board as shown.

We introduce the riht input and output pins. Please refer to Digilent Spartan 3 Starter kit manual.

We are now ready to save Constraints in File -> Save Constraints as shown:

Leave PlanAhead with File ->  Exit

Press OK as in following window:

We are now back to Project Navigator where we will see our constraints file we have just created:

We wii proceed to Processes window and run Synthetize-XST as shown:

Hopefully results will be of sucessful synthesis:

We next will run Implement Design:

And the results will be again hopefully of sucessful process:

Finally we are ready to generate the bit file with which we will program our Digilent Spartan 3 Starter kit board:

Programming file will be generated hopefully:

And the Console window will show the results of the process:

The right window of our Project Navigator will give us the summary of our project:

We are finally ready to implement after checking out the summary that everything is right.

We will now program in our Spartan 3 board. It is assumed that you have the Digilent board duly configured to “see” the USB Jtag programming cable, and Digilent Adept 2 chaintool is installed in your PC.

Within Processes window choose Generate Programminf file. Right click with your mouse and Run as shown

Programming file will be generated hopefully with success:

Finally we will program our Digilent Spartan 3 Starter kit board:

A pop up window will open:

Click OK. Xilinx ISE Impact will open with empty workspace:

Double click on Boundary Scan. The empty workspace will now show:

Do as it says: Right click to initialize toolchain. Choose the option as shown below:

The result will be:

A sucessful identification has occured. Press Yes button.

NOTE: We will not program the PROM. This process requires configuration in Adept 2.0 by launching Create PROM file before doing anything else in ISE Project Navigator.

A window will pop up, and we will introduce the bit file we have generated in our Car_Sec project directory.

Assign the bit file and click Open

A new pop up window will invite us to assign PROM file:

Click Bypass. A new window will pop up:

Press OK and the result will be:

We will now right click XC3S200 icon in order to program the board and choose Program:

Device will be programmed and hopefully will be hopefully successful as shown below

A succesful programming has been done.

Testing the project

The alarm security circuit will light up a LED (LD0) on Spartan 3 Starter kit board, simulating SIREN sounding, only when the conditions we have established of state machine occurs. Test the state machine as shown:

On Digilent Spartan 3 board, the leftmost switch represents ALARM armed or unarmed (upward or downward respectively) the rightmost switches are DOOR (upward door open, downward door closed) and ULTRASONIC SENSOR (upward presence detected and downward no presence).

DEMO Video:

Download

The board Constraints and bit file can be downloaded from here.

Conclusions:

A complete Workflow has been shown in this three parts tutorial of a simple Car Security Alarm using Finite-State Machine to design the logic circuit.

We first designed the State Diagram in StateCAD and generated VHDL, then we simulated our state diagram in StateCAD to verify whether it behaves as expected.

In this part of our tutorial, we imported the VHDL file of part I in Xilinx ISE Project Navigator, and we followed all the procedures to implement our VHDL in an FPGA.

We have sucessfully programmed the Digilent Spartan 3 Starter kit board, and tested our Car Security Alarm state machine we designed in part I.

Objectives

In part I we have generated VHDL code from a State Diagram. We will now simulate the state diagram in order to debug it, and to ensure that it behaves as expected. In part III we will implement the VHDL code of part I in actual FPGA Spartan 3 Starter kit board.

Using Statebench

Before implementing our logic in our Spartan 3 Board we need to make sure that the State Diagram that we have designed will be behaving as expected by simulating it. With StateBench we can go through our design one clock cycle at a time, changing inputs and verifying outputs.

Our State Diagram of part I looks like this:

In order to be able to simulate it, we need to add a reset. In StateCAD activate Add reset:

Now add reset to the state diagram:

The following window will pop up:

Press No button to choose synchronous. We are now ready to simulate.

Click the StateBench button:

StateBench window will open:

Click the Reset button. We will now see the initial state:

We then need to add more clock cycles, clicking onto:

The result will be as shown:

We will next change input by double clicking on a time line position of input and a cursor line will appear as shown with a pop up window to assign a value:

Change the value to decimal 1 (001). The resulting window will pop up:

We will choose No to change input value to 001 henceforth. And the result will be:

NOTE: By default the rightmost edge of the clock before the point chosen will be indicating the new value (decimal 1). SIREN is still off, and we remain in STATE0.

Change values the same way to 2 (010) , 3 (011) and 4 (100). The state will continue to be STATE0 and SIREN will not sound, i.e. it will be 0 (zero).

Nowzn if we add input value 5 (101) at a different time line as shown:

The following window will pop up:

Choose again No to change values henceforth.

Around less than 10 cycles later (about 1ms later) there will a transition to STATE1 and SIREN will be sounding. i.e. it will be 1. To view better the transition, add more clock cycles by  clicking onto:

And now you can view better what is happening:

Change again by double clicking at time line edge of input to obtain the following result:

Introduce 4 (100) i.e. door is closed (B=0) and again the following window will pop up:

Choose No to maintain the input value henceforth. The result will be as shown i.e. that the state remains itself as STATE1 and SIREN is still sounding:

The graph means that if we rapidly shut the door (returning to 100 condition)  at 86ns (1300 minus 1214ns)  the SIREN will continue to sound, and the system will maintain itself at STATE1. Change the condition again to another value as shown:

Now at a different time line do the same procedure as before and change the condition of input to 1 (001)

To view bettera, add clock cycles by pressing the button:

Our better view will be something similar to shown below:

At about less than 10 cycles i.e. about 1ms, there will be transition to STATE0 and SIREN will not sound anymore. We have returned to the first state, i.e. STATE0. If we repeat the input conditions as we did before, we will prove that a transition occurs only to STATE1 when input is either 5 (101) or 6 (110)  or 7 (111).

Conclusions:

StateBench allows to simulate a state diagram by going through our design one clock cycle at a time, changing inputs and verifying output.

Our simulation has proven that the State Diagram we designed in part I is behaving as expected. We need now to implement and to test in our Digilent Spartan 3 board, the VHDL we generated in part I..

Objectives

Finite-state machine (FSM) or finite-state automaton design of a simple car security alarm using StateCAD, and implementation  on a Digilent FPGA Spartan 3 Starter kit board..

In this part we will generate the VHDL code. In part II we will simulate and in part III we will implement the VHDL code in our Digilent Spartan 3 Starter kit board.

Requirements

– StateCAD inside Xilinx ISE Design Suite 10.1
– Digilent Spartan 3 Starter Kit board (for implmentation in part II)

Overview

StateCAD allows visual implementation of a State Diagram and translation into a Hardware Description Language (HDL) code. It is not necessary to understand the HDL code, however we have little control over how the software translates the state diagram.

We will create a state diagram for a car security alarm, and generate VHDL.  In part II we will simulate our state diagram to check whether it behaves like we expect. In part III we will create the schematic symbol and implement the VHDL code in our Diglent Spartan 3 board, and finally test the car security alarm to ensure that it works as expected.

Car Security Alarm Specifications

We wil devise a simple Car Security Alarm that will sound a siren if the car alarm system has been energized i.e. armed (A=1) and the door is open (B=1) and / or an ultrasoic sensor signals movement inside the car (C=1).

Image showing door switch , ultrasonic sensor and siren

We need to ensure that when the door has been opened in an unauthorized manner, or a presence is detected by the ultrasonic sensor within the car, the alarm siren will sound. This is achieved with a Finite-State Machine (FSM) as shown:

State transition diagram of car security alarm

1) In STATE0 the siren is off (SIREN=0) if the alarm is not energized that is armed (A=0) and the door (B) or the ultrasonic sensor (C) can be in any combination, or if alarm is armed (A=1) the siren will not sound if door is closed (B=0) or no presence is detected within the car by the utlrasonic sensor (C=0).

2) There is a transition from STATE0 to STATE1. if alarm is armed (A=1) and if either the door is open (B=1) or ultrasonic sensor detects a presence within the car (C=1) or both the door is open and ultrasonic sesnor detects (B=1 and C=1), the siren  will sound, and the system will remain in STATE1.

3) The system will remain in STATE1 that is. siren will be sounding whatever happens next to the door (either is closed or open or sensor detects or not, provided the alarm is still armed (A=1).

4) Transition from STATE1 to STATE0 occurs only if the system is desarmed (A=0). and in this circunstance for B or C, the siren will not sound anymore (SIREN=0).

Creating the Diagram in StateCAD

Our aim is to obtain a State Diagram as shown above.

Open StateCAD by navigating thorugh the Start menu:  Start -> Programs -> Xlinix ISE Design Suite 10.1 -> ISE -> Accessories -> StateCAD.

Activate the state diagram tool by clicking the Add State icon found  in the tool bar:

A state similar to the one shown below appears:

You will draw next State as shown in our proposal for the State Diagram. We will next connect up the two states with transitions by using the tool Add Transition, activating the following icon in the tool bar:

 And now draw by clicking and linking to obtain the following result:

Both states and transitions

Save the drawing with the name STATE_CAR. Now click onto the STATE0 and Edit State window will pop up:

Output condition  SIREN=”0″ added

Do as shown introducing output SIREN=”0″. After finishing click OK, and do the same with STATE1 and add output condtion as SIREN =”1″

Add variable vector to the drawing by activating Add Vector icon (looking like a yellow bus) in the tool bar:

And place variable vector:

Click onto it  and the Edit Vector window will pop up:

Change the name to ABC and the range to 2:0, as shown in the figure and click OK.

We will next change the conditions of the transitions. Click onto the loop back transition of STATE0 and Edit Condition window will pop up:

Introduce Condition: ABC = “000”) OR (ABC=”001″) OR (ABC=”010″) OR (ABC=”011″) OR (ABC=”100″) . And press OK

Edit all other transitions to obtain the following final result:

We are now ready to ckeck variables. Right click with the mouse onto an empty area of the drawing and the follwing menu will pop up where you will choose Variable… .:

Menu to check the variables

The window with Variables will pop up:

Variables window

If you have done everything right the window will show all the variables in your drawing. Click OK.

NOTE: You can make modifications here if it is required.

We are now ready to compile.  Click Generate VHDL icon on top tool bar just below top menu:

If everything is OK, following window will pop up:

NOTE: Warning windows may pop up before Results, to tell you for example that compilation has found remnants of variables you may have added and invitate you to delete them, that you must do.

A window will pop up if you Close the window, showing the VHDL code that has been generated:

Generated code window

NOTE. You can check now if the code makes sense, but can do nothing else apart going back to  the drawn project and edit it.

We are just about ready to simulate the state diagram and implement the VDL code in our Xilinx FPGA, something that we will do in parts II and III of this tutorial.

Download

The drawing and generated VHDL files can be downloaded from here.

Acknowledgements

A special credit is due to Examples from Class pdf found at University of Wrocester site, for the state diagram. This tutorial uses a  completely different approach to achieve the code generation.

Conclusions

We have designed  a State Diagram in StateCAD and compiled a VHDL file. In part II we will simulate the state diagram and in part III we will program our Digilent Spartan 3 board, and test physically the logic circuit.